`timescale 1 ns / 100 ps
module sdpram_byteena_lpm #(

parameter   A_ADDRESS_WIDTH =  10,
parameter   A_DATA_WIDTH = 8,
parameter   A_BYTEENA_WIDTH = 1,
parameter   B_ADDRESS_WIDTH =   8,
parameter   B_DATA_WIDTH =  32) 
(

input   wire                            clka,
input   wire                            wea,
input   wire    [A_ADDRESS_WIDTH-1:0]   addra,
input   wire    [A_DATA_WIDTH-1:0]      dina,
input   wire    [A_BYTEENA_WIDTH-1:0]   byteena_a,

input   wire                            clkb,
input   wire                            reb,
input   wire    [B_ADDRESS_WIDTH-1:0]   addrb,
output  wire    [B_DATA_WIDTH-1:0]      doutb
);


wire [B_DATA_WIDTH-1:0] sub_wire1;
assign    doutb = sub_wire1;

    altsyncram  altsyncram_component (
                .clock0 (clka),
                .wren_a (wea),
                .rden_a (1'b1),
                .data_a (dina),
                .address_a (addra),
                .q_a (),
                .byteena_a (byteena_a),
                
                .clock1 (clkb),
                .wren_b (1'b0),
                .rden_b (reb),
                .address_b (addrb),
                .data_b ({B_DATA_WIDTH{1'b1}}),
                .q_b (sub_wire1),
                .byteena_b (1'b1),
                
                .aclr0 (1'b0),
                .aclr1 (1'b0),
                .addressstall_a (1'b0),
                .addressstall_b (1'b0),

                .clocken0 (1'b1),
                .clocken1 (1'b1),
                .clocken2 (1'b1),
                .clocken3 (1'b1),
                .eccstatus ()
                );
    defparam
        altsyncram_component.address_reg_b = "CLOCK1",
        altsyncram_component.clock_enable_input_a = "BYPASS",
        altsyncram_component.clock_enable_input_b = "BYPASS",
        altsyncram_component.clock_enable_output_a = "BYPASS",
        altsyncram_component.clock_enable_output_b = "BYPASS",
        altsyncram_component.intended_device_family = "Cyclone IV E",
        altsyncram_component.lpm_type = "altsyncram",
        altsyncram_component.numwords_a = 2**A_ADDRESS_WIDTH,
        altsyncram_component.numwords_b = 2**B_ADDRESS_WIDTH,
        altsyncram_component.operation_mode = "DUAL_PORT",
        altsyncram_component.outdata_aclr_a = "NONE",
        altsyncram_component.outdata_aclr_b = "NONE",
        altsyncram_component.outdata_reg_b = "CLOCK1",
        altsyncram_component.power_up_uninitialized = "FALSE",
        altsyncram_component.rdcontrol_reg_b = "CLOCK1",
        altsyncram_component.widthad_a = A_ADDRESS_WIDTH,
        altsyncram_component.widthad_b = B_ADDRESS_WIDTH,
        altsyncram_component.width_a = A_DATA_WIDTH,
        altsyncram_component.width_b = B_DATA_WIDTH,
        altsyncram_component.width_byteena_a = A_BYTEENA_WIDTH,
        altsyncram_component.width_byteena_b = 1;



endmodule